The present invention relates generally to voltage regulation, and more particularly to a low drop-out (LDO) voltage regulator with a split power device.
A low drop-out (LDO) regulator is a linear regulator which utilizes a transistor or FET to generate a regulated output voltage with very low differential between the input voltage and the output voltage. LDOs are often used in battery powered devices. In such applications, in order to minimize the current drain under light loads, it is common to have an xe2x80x9cSLEEPxe2x80x9d mode for the regulator in which the maximum load current is limited to a few milliamps and the quiescent current is very low, approximately 10-20 microamps. In the normal or xe2x80x9cONxe2x80x9d mode, the normal load current can be a few hundred milliamps which requires a regulator having a higher bias current, as much as 100 microamps.
FIG. 1 illustrates FIG. 2 of the parent application. The application simplifies the construction of the regulator by utilizing a split output of the driver so that a relatively small power transistor is utilized in the low power or SLEEP mode and a larger device or both devices are used in the normal ON mode. FIG. 1 shows the LDO shown in FIG. 2 of the copending application generally as 100. An error amplifier 104 has its inverting input 106 coupled to a reference source VREF and its non-inverting input 108 coupled to a sample of the output voltage at node 188 via voltage divider 186, 190 and fed back via line 196. The output of the error amplifier 104 is fed into a second amplifier 111, the output of which is input to the non-inverting input of unity gain buffer amplifier 118. The output of this amplifier is split so that OUTPUT_2 on line 120 is coupled to the gate of large transistor 156 and the output 1 on line 122 is coupled to the gate of the small transistor 150. OUTPUT_1 is also coupled to the inverting input of amplifier 118. PMOS transistors 150 and 156 each have a source coupled to VDD at line 102 and a drain coupled to the output voltage at node 160. A Miller capacitor 162 is coupled from the output node 160 to the input 110 of the amplifier 111 via line 114. A resistor 192 in series with filter capacitor 194 is placed in parallel with load 198 between the output voltage at 160 and ground. A switch 123 is coupled between VDD and the gate of transistor 156. A switch 124 is coupled between the transistor 156 and the gate of transistor 150. The operation of the switch is determined where the circuit operates in the SLEEP mode or the normal ON mode. The switches are controlled via an external signal (not shown), although the specification discloses that it is possible to detect the load current level and have the LDO automatically switch modes.
It is a general object of the present invention to provide an LDO that switches automatically from SLEEP to ON modes.
This and other objects and features are attained, in accordance with one aspect of the invention, by a low drop-out voltage regulator, comprising an input error amplifier stage. A first amplifier stage has a first output, a first input coupled to an output of the input error amplifier stage and a second input coupled to a first bias source. A second amplifier stage has a second output, a third input coupled to the output of the input error stage and a fourth input coupled to a second bias source. A first power transistor has a gate coupled to the first output, the first power transistor also being coupled to a node where voltage is to be regulated. A second power transistor has a gate coupled to the second output, the second power transistor also being coupled to the node; wherein an output voltage of the first bias voltage source differs from an output voltage of the second bias voltage source by a predetermined voltage, whereby the first amplifier stage and the first power transistor are active at a first output current range and both the first amplifier stage and first power transistor and second amplifier stage and second power transistor are active at an output current that exceeds the first output current range.
A second aspect of the invention includes a low drop-out voltage regulator comprising an input error amplifier stage. A first amplifier stage has a first output, a first input coupled to an output of the input error amplifier stage. A second amplifier stage has a second output, a third input coupled to the output of the input error stage, wherein the input error amplifier stage, the first and second amplifier stages each have a bias input coupled to a threshold detection circuit. A first power transistor has a gate coupled to the first output, the first power transistor also being coupled to a node where voltage is to be regulated. A second power transistor has a gate coupled to the second output, the second power transistor also being coupled to the node wherein the threshold detection circuit determines if output current of the regulator exceeds a second output current range and adjusts a bias input to at least one of the input error amplifier stages, the first amplifier stage and the second amplifier stage when the output current exceeds the second output current.
A third aspect of the invention comprises a low drop out regulator comprising a first power transistor having a gate and being coupled to a node where voltage is to be regulated. A first drive stage receives a feedback signal from the node and is coupled to the gate of the first power transistor for regulating the voltage at the node when output current of the regulator is below a predetermined level. A second power transistor has a gate and is coupled to the node. A second drive stage receives the feedback signal and is coupled to the gate of the second power transistor for regulating the voltage at the node when output current of the regulator exceeds the predetermined level, wherein the second drive stage and the second power transistor are active only when the output current exceeds the predetermined level, the second drive stage being activated to drive the second power transistor by the feedback signal only, without a control signal generated external to the regulator.
A fourth aspect of the invention is provided by a low drop-out regulator comprising a first current path between an input voltage and a regulated output voltage at an output node. A second current path between an input voltage and the regulated output voltage at the node, wherein the first current path is active in a low current mode in which output current is below a predetermined level and at least the second current path is active in a high current mode in which the output current exceeds the predetermined level, the regulator switching from the low current mode to the high current mode without a control signal generated external to the regulator.